Work

Swap on Sky: A Skyrmion-Based In-Memory Swapping Architecture to Break Memory Wall

Year: 2025

Type: article

Abstract: Swapping operations, fundamental to algorithms in sorting, searching, graph processing, and machine learning, incur substantial data movement overhead between the CPU and host main memory due to the memory wall. Traditionally, swapping necessitates loading two elements from memory into CPU registers, performing the swap, and writing these elements back to their memory locations. This cycle of data transfer introduces significant latency caused by memory access delays and data movement overhead. To overcome this challenge, Computing-in-Memory (CiM) technologies have been proposed, enabling direct data manipulation within memory to eliminate costly CPU-memory transfers. Skyrmion Racetrack Memory (SKRM), an innovative non-volatile memory technology, is particularly suitable for implementing in-memory swapping due to its unique operational advantages. Unlike conventional DRAM, SKRM stores data as movable magnetic domains (skyrmions) along nanotracks, allowing data positions to be shifted efficiently through current pulses without physically transferring data outside memory. This inherent characteristic substantially reduces energy consumption and latency compared to DRAM, which demands explicit read and write operations for swapping. This article enables an optimized SKRM-based in-memory swapping mechanism, which not only realizes in-memory swapping to break the memory wall but also jointly considers the costs associated with skyrmion creation and shifting, further enhancing performance and energy efficiency. To demonstrate the effectiveness of our solution, we integrate it into a decision tree-based machine learning framework, emphasizing the frequent swapping operations essential in decision tree construction. Experimental evaluations demonstrate promising results, highlighting significant reductions in both energy consumption and memory access latency.

Source: ACM Transactions on Architecture and Code Optimization

DOI: 10.1145/3779225

Authors: Sin Chen, Yikai Huang, Yao-Yu Liao, Tseng-Y Chen

Institution: National Central University

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: diamond

Funder: National Science and Technology Council