Work

The impact of Back-Gate biasing and layout on temperature sensitivity of transistors in FD-SOI CMOS technology

Year: 2025

Type: conference-paper

Source: IEEE International Conference on ASIC (ASICON)

DOI: 10.1109/asicon66040.2025.11326183

Authors: Yann Deval, Maxime Guillot, Hervé Lapuyade, François Rivet

Institutions: Centre National de la Recherche Scientifique, Université de Bordeaux, Laboratoire de l'Intégration du Matériau au Système, Institut Polytechnique de Bordeaux

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4416980797

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