Work

Cache partitioning for sparse matrix–vector multiplication on the A64FX

Year: 2025

Type: article

Abstract: One of the novel features of the Fujitsu A64FX CPU is the sector cache . This feature enables hardware-supported partitioning of the L1 and L2 caches and allows the programmer control of which partition is used to place data in. This paper performs an in-depth study of applying the sector cache to sparse matrix-vector multiplication (SpMV) in the Compressed Sparse Row (CSR) format using a collection of 490 sparse matrices. A performance model based on reuse analysis is used to better understand situations in which and how the sector cache leads to improved cache reuse and to predict cache behavior. The model predicts the number of L2 cache misses within an error of 2% without cache partitioning. With sector cache enabled, depending on the configuration, the model predicts the number of L2 cache missed within 2–3% and 4–18% for sequential and parallel SpMV with 48 threads, respectively. Further experiments show the effect of various sector cache configurations on performance. A median speedup of about 1.05 × is achieved, whereas the maximum speedup is about 1.6 × .

Source: Parallel Computing

DOI: 10.1016/j.parco.2025.103169

Authors: Sergej Breiter, James D. Trotter, Karl Fürlinger

Institutions: Ludwig-Maximilians-Universität München, Simula Research Laboratory

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

Estimated APC paid: $2,870

Funders: Bundesministerium für Bildung und Forschung, Norges Forskningsråd, Leibniz-Rechenzentrum