Year: 2025
Type: article
Abstract: ABSTRACT The increasing demand for ultra‐low‐power and high‐performance memory systems in Internet of Things (IoT) applications necessitates the exploration of advanced SRAM architectures. FinFET technology, with its superior electrostatic control and reduced leakage current (I_Leakage), has emerged as a promising solution at sub‐45 nm nodes. This paper presents a detailed comparative analysis of FinFET‐based 7‐transistor and 8‐transistor static random access memory (SRAM) cells, focusing on parameters like power consumption, delay and power‐delay product. This comprehensive analysis aims to provide insights into optimizing SRAM cell architectures for future IoT applications, ensuring reliability and efficiency in data storage and retrieval. The 7T FinFET SRAM design demonstrates a reduction in average power dissipation of approximately 38% and an increase in average noise voltage of about 8% when compared to 8T SRAM cells. Cadence Virtuoso ADE serves as the primary tool for all design and simulation activities. The results demonstrate the trade‐offs involved in cell design, providing insight into the suitability of each architecture for edge IoT devices.
Source: Internet Technology Letters
DOI: 10.1002/itl2.70205
Authors: Deepak Garg, Devendra Kumar Sharma, Lalit Garg
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4417142706