Enabling Confidential I/O on RISC-V Without Hardware Modifications
Year: 2025
Type: conference-paper
Abstract: Despite the increasing complexity of operating systems and drivers, TEEs have been a reasonable option for protecting security-critical software from certain adversaries. However, increasing complexity and heterogeneity characterize the hardware side, too, with designers relying on accelerators and sensors to continue delivering performance gains and novel features. These accelerators and sensors often handle data which should be secured in some way; system integrators would therefore like to enforce confidentiality, integrity, or availability properties on them. Confidential I/O systems are able to enforce these properties at some performance cost, and can be built on top of various standard isolation primitives. Prior work has built such systems primarily on Intel and ARMv8 CPUs, but comparable functionality is currently missing on emerging RISC-V platforms.
Authors: Gregor Haas, Micheal Chung, David Kohlbrenner
Institution: University of Washington
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4417223142