Work

Video Action Recognition in SoC FPGAs Driven by Neural Architecture Search

Year: 2025

Type: conference-paper

Abstract: This work presents a hardware-aware Neural Architecture Search (NAS) framework for video-based human action recognition, targeting real-time deployment on FPGAbased System-on-Chip (SoC) platforms. The proposed method explores a constrained search space of Convolutional Neural Network (CNN)-Recurrent Neural Network (RNN) architectures aligned with a hardware-software pipeline where CNNs are mapped to FPGA Deep Learning Processing Units (DPUs) and RNNs to embedded ARM cores. A reinforcement learning (RL)-based controller, guided by a position-based discounted reward strategy, progressively learns to generate architectures that emphasize high-impact design decisions. Experiments on the UCF101 dataset demonstrate that the proposed architectures achieve 81.07 % accuracy, among the highest reported for CNNRNN models relying exclusively on spatial information. The results validate the effectiveness of the proposed framework in driving hardware-compatible and performance-optimized architecture exploration.

Source: Conference on Design of Circuits and Integrated Systems

DOI: 10.1109/dcis67520.2025.11281932

Authors: Daniel Suárez, Pedro Hernández-Fernández, Víctor Fernández, Gustavo M. Callico

Institutions: Universidad de Cantabria, Universidad de Las Palmas de Gran Canaria

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

Funders: Ministerio de Ciencia, Innovación y Universidades, European Commission, European Regional Development Fund, Agencia Estatal de Investigación

OpenAlex ID: W4417249379