Year: 2025
Type: conference-paper
Abstract: Modern data-intensive applications face memory latency challenges exacerbated by disaggregated memory systems. Recent work shows that coroutines are promising in effectively interleaving tasks and hiding memory latency, but they struggle to balance latency-hiding efficiency with runtime overhead. We present CoroAMU, a hardware-software co-designed system for memory-centric coroutines. It introduces compiler procedures that optimize coroutine code generation, minimize context, and coalesce requests, paired with a simple interface. With hardware support of decoupled memory operations, we enhance the Asynchronous Memory Unit to further exploit dynamic coroutine schedulers by coroutine-specific memory operations and a novel memory-guided branch prediction mechanism. It is implemented with LLVM and open-source XiangShan RISCV processor over the FPGA platform. Experiments demonstrate that the CoroAMU compiler achieves a $\mathbf{1. 5 1} \boldsymbol{\times}$ speedup over state-of-the-art coroutine methods on Intel server processors. When combined with optimized hardware of decoupled memory access, it delivers $3.39 \times$ and $4.87 \times$ average performance improvements over the baseline processor on FPGA-emulated disaggregated systems under 200 ns and 800 ns latency respectively.
Authors: Zhuolun Jiang, Songyue Wang, Xiaokun Pei, Tianyue, Mingyu Chen
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4417403177
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