Work

Fast RISC-V Firmware Validation with QEMU

Year: 2024

Type: article

Abstract: We present a flexible, system-level/RTL co-simulation approach that utilises existing design artefacts, such as RTL descriptions of peripherals, as well as the device tree of an SoC (e.g. the Rocket Chip Generator), to generate simulation models and configure a QEMU simulation. Such a simulation makes it possible to evaluate hardware/software systems, particularly the effectiveness of the integrated safety mechanism targeted by ISOLDE.

Source: Zenodo (CERN European Organization for Nuclear Research)

DOI: 10.5281/zenodo.15535716

Author: Haxel, Frederik

Institution: FZI Research Center for Information Technology

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

Funder: European Commission

Award: High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems