Enhanced Carrier Level Shifted PWM Technique for Capacitor Voltage Balance in Five-Level DCMLI
Year: 2026
Type: article
Abstract: An Inherent problem with the Diode Clamped Multi Level Inverter is the unbalance in capacitor voltages. This unbalance may lead the inverter to have uneven levels of output voltage and more THD as compared to the expected. Therefore, the stabilization of neutral point voltage is the major task to get expected voltage and the desired levels. There are techniques, which are reliable for the neutral point stabilization of three-level diode clamped multilevel inverters, but there is no specific reliable technique, which would provide inherent stabilization of capacitor junction voltages in the five-level diode clamped multilevel inverters. Existing techniques use either back to back connection of five-level inverter-rectifier or use separate DC sources (SDCS). These methods use extra components and are complex to implement. To overcome this problem a new inherent control technique entitled as ‘Enhanced Carrier Level Shifted PWM Technique’ is recommended in this paper to stabilize the capacitor junctions in five-level diode clamped multilevel inverter (DCMLI).
Authors: K. Narasimha Raju, P. Siva Sankar, CH. S.Balasubrahmanyam, B. Sai Sandeep Babu
Institution: Koneru Lakshmaiah Education Foundation
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W6942463406
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