Work

On-chip Digital Calibration of Low-voltage Operational Amplifier in CMOS

Year: 2025

Type: article

Abstract: This paper proposes an analysis of digital method of input offset compensation in operational amplifier, integrated as a single system in 130 nm CMOS technology. The whole system operates with 0.6 V supply voltage and consumes less than 80 µW of power. The paper includes small-signal analysis investigating possible adverse effects of added calibration hardware on the calibrated amplifier. Proposed solution was verified through Monte Carlo simulations in temperature range from −20°C to85°C in Cadence design environment. Using the proposed method of calibration, the input offset voltage of operational amplifier was suppressed from 278 µV to 22 µV (in terms of mean value).

Source: Zenodo (CERN European Organization for Nuclear Research)

DOI: 10.5281/zenodo.15166002

Authors: Sovcik, Michal, Arbet, Daniel, Nagy, Lukas, Stopjakova, Viera

Institution: Slovak University of Technology in Bratislava

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W6949512199

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