Work

Interconnection Optimization: A Treasure Trove for the EDA of Digital Electronic Circuits

Year: 2025
Type: conference-paper
Abstract: As Moore's Law approaches physical limits, optimizing interconnection complexity emerges as a key opportunity in VLSI. Our findings reveal that by measuring and controlling Rent's exponent—a key indicator of interconnection complexity—in FPGA netlists, metrics like runtime, wirelength, and critical path length exhibit a double-exponential relationship with complexity. This underscores the potential of interconnection as a resource for optimization. Based on these insights, strategies such as sparse packing and duplication can simplify the interconnection structure with acceptable circuit size sacrifice, ultimately enhancing EDA physical design efficiency.
Author: Xiaoke Wang
Language: English
Open Access status: green
OpenAlex ID: W6967993136
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