Soft Digital Signal Processing
Year: 2025
Type: article
Abstract: In this paper, we present a framework for low-energy digital signal processing (DSP) in which the supply voltage isscaled above the critical voltage required to match the critical path delay to the throughput. The deliberate insertion of inputdependent defects degrades algorithmic performance, which is compensated by using algorithmic noise tolerance (ANT)techniques. The resulting arrangement, which includes the DSP architecture working at subcritical voltage and the errormanagement mechanism, is referred to as soft DSP. Using arithmetic units with a higher "delay imbalance" improves the suggestedscheme's effectiveness. A prediction-based error-control technique is developed to improve the filtering algorithm's performancewhen soft computation errors occur. For a frequency selective filter, the proposed scheme reduces energy dissipation by 60-81%for filter bandwidths up to 0.5 (where 2 is the sampling frequency) compared to conventional architecture and voltage scaling,with a maximum 0.5-dB degradation in output signal-to-noise ratio (SNR). It is also shown that the proposed algorithmic noisetolerance schemes can also be used to improve the performance of DSP algorithms in presence of bit-error rates of up to 10 3 dueto deep submicron (DSM) noise.
Author: K Haritha, P.Meenakshi, R.Sasi
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W6968386264
FWCI:
Cites:
Cited by:
Related to: