Work

Exploiting instruction- and data-level parallelism

Year: 1997

Type: article

Abstract: Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.

Source: IEEE Micro

DOI: 10.1109/40.621210

Authors: R. Espasa, M. Valero

Institution: Universitat Politècnica de Catalunya

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W2113125938

FWCI: 2.174

Cites: 15

Cited by: 41

Related to: 10