Verbeteren van Software-geïmplementeerde Hardwarefouttolerantie voor Embedded Systemen
Year: 2024
Type: dissertation
Abstract: In modern programmable systems, factors like higher component density, lower voltage levels, and an increased number of transistors have amplified the susceptibility of embedded systems to transient bitflip faults. These faults can occur due to external disturbances such as radiation or electromagnetic interference. This electromagnetic interference can be both conducted or radiated. These soft errors often pass unnoticed, but their consequences can be severe since they lead to unpredictable system behavior. Specifically, two types of errors emerge, namely corruption of data (Data Flow Errors, DFEs) and unintended jumps in the program flow (Control Flow Errors, CFEs). Given the adoption of such systems in safety-critical and mission-critical applications, ensuring their reliability becomes paramount. To mitigate the impact of bitflips, researchers have explored Software-Implemented Hardware Fault Tolerance (SIHFT) techniques. Unlike traditional hardware-based approaches, SIHFT aims to detect errors caused by transient faults directly within the software. By introducing redundant instructions to verify the program state, SIHFT techniques can identify corrupted data and control flow anomalies at runtime. However, much of the existing research focuses on simplified scenarios. These techniques struggle to scale up for larger, more realistic applications, making their adoption challenging or even impossible. We investigated the limitations of state-of-the-art SIHFT techniques when applied to large case studies. We identified that many of the major techniques could not be applied to real-world applications due to their reliance on a large number of dedicated CPU registers. More specifically, instruction duplication techniques - one of the most prominent error detection techniques in the state-of-the-art - need these registers to store redundant values. Unfortunately, this can cause a shortage of available registers, leading to a compilation failure for real-world applications. To solve this issue, we propose a set of SIHFT techniques that can reliably detect both DFEs and CFEs while merely utilizing three dedicated CPU registers. Opposed to the classical instruction duplication approach, our techniques rely on re-execution and checkpointing to detect bitflips. While the state-of-the-art DFE detection techniques fail to compile for numerous of our case studies, the techniques developed in this thesis can be implemented for all applications, regardless of their size or complexity. The proposed techniques were rigorously evaluated through extensive fault injection campaigns across various case studies, showcasing their effectiveness. Comparing our techniques to existing state-of-the-art methods, we found that they achieve a comparable error detection ratio for both DFEs and CFEs. The novel techniques effectively cover errors that cause unpredictable system behavior while disregarding faults with no impact on system functionality. However, the evaluation also shows that the re-execution-based approach can lead to considerable overhead in execution time and program size for certain applications. To address the high overhead, firstly, the well-known strategy of selective implementation was used. In this approach, only a selection of the CPU registers are protected as opposed to all of them. Secondly, the possibilities of SIHFT extensions for the rising open-source RISC-V instruction set architecture were explored. Due to the extendable nature of RISC-V, new possibilities for developing optimized, reliable, and secure systems arise. As a step toward adopting software-implemented tolerance techniques within the RISC-V ecosystem, this thesis proposes a specialized RISC-V extension that supports one of our re-execution-based techniques. While SIHFT techniques can be implemented on any processor architecture, the RISC-V extension offers a more efficient implementation, promising significantly reduced overhead without impacting error detection rates. In addition to the novel SIHFT techniques, we provide tool support to facilitate the adoption of these techniques in the form of a publicly available GCC plugin under a GPL license model. This plugin allows developers to easily apply the proposed SIHFT techniques, as well as numerous state-of-the-art techniques to their applications. The plugin supports multiple target architectures and is designed to be easily extendable to provide support for other target architectures and SIHFT techniques. By providing new SIHFT techniques that can be applied to real-world applications and providing the tool support to implement these techniques, this thesis aims to make SIHFT techniques more accessible to the broader software engineering community.
Source: Lirias
Author: De Blaere, Brent
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7044172934
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