Design of 6T SRAM Memory Array and Read, Write Separation based Sleep Transistor for IOT Applications
Year: 2025
Type: article
Abstract: Nowadays optimization of power is a majorChallenge in VLSI industry. As the density of the memory systems increases, the power consumption also increases.SRAM cell is most fundamental component for all the memory devices like cache memories and CPU registers etc. The leakagecurrent of a transistor also leads to more power consumption.So there is a need to reduce the power consumption in each cell of a memory. This problem is avoided in SRAM memory cell. Hence it's essential to possess energy- efficient present circuit static memory which focuses on optimizing delay and power. .The olden days SRAM cell consumed more power and produces more delay. To decrease the power consumption and time, the introduced 6T SRAM cell separates read and write operation. The proposed SRAM array is designed using micro wind (45nm) and the power measured as 287mW,and delay is 20.89μs,
Authors: Choudhary, Bipin Kumar, Soni, Braj Bihari
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7075852534
FWCI:
Cites:
Cited by:
Related to: