Work

A Fractional-N Cascaded PLL With MMD-Based Quantization-Error Cancellation

Year: 2025

Type: article

Abstract: A fractional-N phase-locked loop (PLL) with cascaded architecture is presented. Compared to the conventional cascaded PLL, an auxiliary multi-modulus divider (MMD) is added between the first-stage integer-N PLL and the second-stage fractional-N PLL. This auxiliary MMD shares the same delta-sigma modulator (DSM) with the main MMD in the second-stage loop. Analysis shows that the two quantization errors (Q-errors) at the auxiliary and main MMD outputs are nearly identical, and the overall Q-error is canceled by a factor ofN. A proof-of-concept prototype is implemented in 65-nm CMOS technology, and the effectiveness of the proposed technique is demonstrated through measurement results, where both the quantization noise (Q-noise) and the in-band fractional spurs arising from the PD nonlinearity are effectively suppressed. With an 82 MHz reference, the PLL achieves 96 fs RMS jitter and −70.6 dBc worst-case in-band fractional spur while consuming 21.2 mW, leading to a FoM of −247.1 dB, without any calibration.

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/jssc.2025.3595657

Authors: Haoming Zhang, Yuyang Zhu, Masaru Osada, Tetsuya Iizuka

Institution: The University of Tokyo

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

Estimated APC paid: $2,645

Funders: Japan Science and Technology Corporation, Murata Science Foundation