Work

On the Evaluation of FPGA-Based Physical Unclonable Functions

Year: 2025

Type: article

Abstract: Physical Unclonable Functions (PUFs) have emerged as a promising hardware security solution, offering robust capabilities for unique device identification and authentication. Their seamless integration, particularly in FPGA-based implementations, makes them especially appealing for resource-constrained devices. However, their widespread adoption is hindered by the inherent challenges of conducting systematic and fair evaluation that considers on-chip experimental data coming from a large population of devices. To address these challenges, we propose a novel evaluation-system for the automated characterization of FPGA-based PUFs. This system provides a comprehensive suite of tools that enable the efficient assessment and detailed analysis of key PUF properties, such as uniqueness and reliability, across a substantial number of physical devices. Furthermore, the system supports the whole lifecycle of PUF development, encompassing both the design and implementation of diverse PUF architectures. This allows end-users to explore, optimize, and seamlessly integrate PUF-based security features into their electronic systems and applications.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2025.3607132

Authors: Daniele Lombardi, Mario Barbareschi, Valentina Casola, Elena Ioana Vatajelu, Giorgio Di Natale

Institutions: University of Naples Federico II, Institut polytechnique de Grenoble, Centre National de la Recherche Scientifique, Techniques of Informatics and Microelectronics for Integrated Systems Architecture, Université Grenoble Alpes

Language: English

Topic: Physical Unclonable Functions (PUFs) and Hardware Security

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: hybrid

Estimated APC paid: $2,645