Work

Performance analysis of dual stacked DRAM for low power embedded devices

Year: 2025

Type: article

Abstract: This work presents a novel dual-stacked silicon/SiGe-based DRAM architecture intended to overcome the constraints of conventional DRAM like scaling, high refresh power and charge leakage. Two vertically stacked layers of silicon and silicon-germanium (SiGe) with 40 % Ge content have been used in the proposed structure to maximize band-to-band tunnelling (BTBT) that has resulted in improved charge storage and retention without the necessity of a large capacitor. Channel engineering of SiGe area in the proposed structure has considerably enhanced the tunnelling rate that has resulted in faster and more effective write and hold operations. Enhanced read reliability is confirmed by a notable sense margin of 6.61 × 10 - 6 A/μm and retention time of approximately 500 ms. The proposed small, capacitorless and energy-efficient DRAM design has successfully demonstrated all the basic DRAM operations like Write '1′, Hold '1′, Read '1′ to verify logic high and then Write '0′, Hold '0′, Read '0′ to confirm logic low, for next generation low power embedded applications.

Source: Microelectronics Journal

DOI: 10.1016/j.mejo.2025.106890

Authors: Rupesh Narayan, Rishu Kumar, Abhishek Raj, Shashi Kant Sharma

Institutions: Indian Institute of Information Technology Ranchi, Indian Institute of Technology Dhanbad, Amrita Vishwa Vidyapeetham

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDGs: Industry, innovation and infrastructure, Affordable and clean energy

Open Access status: hybrid

Estimated APC paid: $2,390