Dynamic adjustment of optimal sampling phase for non-source-synchronous parallel interfaces in FPGA systems
Year: 2025
Type: article
Abstract: Timing misalignment in non-source-synchronous field-programmable gate array (FPGA) interfaces results in significant image degradation in cost-sensitive Contact Image Sensor (CIS) scanners. To address this issue, we propose a Dynamic Adjustment of Optimal Sampling Phase (DAOSP) module, which facilitates autonomous 360° phase scanning with a resolution of 78 ps. The DAOSP utilizes in-situ transition detection and closed-loop adjustment to achieve phase convergence within 5 μs, thereby eliminating the need for iterative FPGA bitstream regeneration. Implemented on Xilinx Artix-7 devices, this solution enables robust data capture at 120 MHz over 10 cm of unshielded cabling (BER<10⁻¹²) with minimal resource utilization (234 LUTs, 479 FFs). Deployed in over 200,000 industrial scanners, the DAOSP enhances the reconstructed image quality by 7.84 dB PSNR while obviating the need for production-line calibration. DAOSP provides a cost-effective, high-precision, and easily integrable solution in the field of FPGA data sampling.
Source: IEICE Electronics Express
Authors: Juhe Ma, Dejun Chen, Huixiong Ruan, Hongyu Jia, Zexin Han, Jieheng Wang, Yong Liu, Ying Luo
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W7082995230