Work

Efficient Extraction and Packing Modules for Posit Multipliers

Year: 2025

Type: article

Source: IEEE Transactions on Circuits & Systems II Express Briefs

DOI: 10.1109/tcsii.2025.3613399

Authors: Tong Li, Honglan Jiang, Zhou Wang, Qin Wang, Jianfei Jiang, Zhigang Mao

Institutions: Shanghai Jiao Tong University, Imperial College London

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W7083184177

FWCI: 0.225

Cites: 11

Cited by: 1

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