Work

Length-Matching-Constrained Chip Routing for via Minimization in RSFQ Circuits

Year: 2025

Type: article

Source: IEEE Transactions on Applied Superconductivity

DOI: 10.1109/tasc.2025.3613953

Author: Jin-Tai Yan

Institution: Tainan National University of the Arts

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W7083185166

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Cites: 31

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