Work

Design And Validation Of Low Power Low Area High Speed Mixed Logic 4 Bit Comparator

Year: 2025

Type: conference-paper

Source: International Conference on Expert Clouds and Applications (ICOECA)

DOI: 10.1109/icoeca66273.2025.00075

Authors: Lohith Reddy Godula, Venkata Sai Jagadeesh Sadu, Siva Ram Gupta Racharla, Harsha Wardhan Reddy Appollu, T. V. V. Satyanarayana

Institution: Mohan Babu University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W7084028638

FWCI:

Cites: 16

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