HiEPAC: High-Throughput and Energy-Efficient SRAM-Based Compute-in-Memory with Parallel Accumulation for DNNs
Year: 2025
Type: preprint
Abstract: The growing demand for efficient deep learning inference on edge platforms necessitates hardware that is both precision-adaptive and resource-efficient. This work presents a highly efficient digital compute-in-memory (DCIM) SRAM macro that accelerates deep neural network (DNN) computations with enhanced energy efficiency, scalability, and throughput. The proposed architecture employs a NOR-enabled 6T SRAM bitcell capable of performing in-situ 4-bit multiplication, seamlessly integrating storage and computation. A sparsity-aware 4:3 compressor with power-gating logic minimizes dynamic power under idle conditions, while a compact 38-transistors PTL-based 4-bit full adder with low logic depth and a hierarchical 64-bit adder tree enable high-parallelism accumulation with reduced critical path latency. A counter-driven shift-and-accumulate (SAC) mechanism ensures correct alignment of partial products, supporting scalable multiply-accumulate (MAC) execution. The 64-bank 64 × 4 CIM array is implemented in 65 nm technology and evaluated using the LeNet-5 model on the MNIST dataset with 4-bit input and weight precision. Circuit-level simulations demonstrate reliable operation across a wide supply voltage range, achieving up to 6.55, 8.19, and 4.10 TOPS throughput at 0.9, 1.0, and 1.1 V with 371, 476, 586 TOPS/W energy efficiency respectively, and a peak efficiency of 586 TOPS/W at 0.9 V while consuming only 6.99 mW. The architecture maintains classification accuracy above 95% with 4-bit quantization, while enabling flexible power management through voltage scaling and bank-level parallelism. Comparative analysis with state-of-the-art digital CIM designs shows superior performance.
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W7084986904
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