Modular Synthesis And Verification Of Timed Circuits Using Automatic Abstraction
Type: article
Authors: Hao Zheng, Reid R. Harrison, Christian Schlegel, Erik Brunvand, Ganesh Gopalakrishnan, Date Chris, J. Myers, V. John Mathews
Language: English
Subfield: Computational Theory and Mathematics
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W7098698838