Design of High-Speed 8-Bit Vedic Multiplier Using Brent-Kung Parallel Prefix Adder
Year: 2025
Type: article
Abstract: One of the primary purposes of a digital signal processing system is multiplication. The multiplier’s performance affects the DSP system’s overall performance. Therefore, it is crucial to create an effective and quick multiplier implementation design. Vedic mathematics can be used to simplify complex computations so that they are easier to perform verbally. Urdhva Tiryagbhyam is the multiplication algorithm used in Vedic math. In this paper, we employ the Brent-Kung adder to enhance the Vedic multiplier’s performance. The Urdhva Tiryagbhyam sutra is used for N×N bit multiplication, producing the least amount of latency. Four 4-bit vedic multipliers, two 8-bit Brent-Kung adders, one 4-bit Brent-Kung adder, and an OR gate are used to create an 8-bit vedic multiplier. Simulation and synthesis were done using EDA Playground software, and results show improved speed compared to related works.
Author: International Journal for Research In Science & Advanced Technologies
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7106543584
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