Exploratie van Latchup in het Design-Technologie en Systeem-Technologie co-optimalisering scaling tijdperk
Year: 2025
Type: dissertation
Abstract: Nowadays the use of advanced technologies is the main driver for the semiconductor industry as they allow to increase functionality for the same chip area. To enable more compute performance per chip several aspects have to be taken into consideration. First, the device scaling can be enabled by using different materials for the channel. Moreover, scaling can be implemented as a device architecture in the frame of design-technology co-optimization (DTCO) for example moving towards complimentary field-effect transistors (CFETs). Other option is a Backside Power Delivery Network (BS-PDN) which decouples the signal and power supply and reduces the parasitics Secondly, scaling effect could be enabled at system level which is referred to system-technology co-optimization (STCO) and can bring additional opportunities to increase the chip functionality. In this work the main aspects of the BS-PDN implementation are introduced. However in most semiconductor qualification latchup (LU) prevails as a high-current issue in complimentary metal-oxide-semiconductor (CMOS) technologies. The activation of a parasitic thyrisor path can lead to a reduced circuit performance or even chip burnout. LU is considered as a well-known issue in mature technologies. However it was not investigated for BS-PDN technology options before. In this work we perform in-depth investigation including measurement and simulation results of the LU issue in BS-PDN options such as sub-um wafer thinning, buried power rail (BPR) and active backside (BS) as BS contacts. Moreover transient-induced LU is covered in this work revealing the impact of different pulse characteristics on LU immunity in BS-PDN. Finally, as one of the STCO applications, LU at cryogenic temperatures is extensively studied in this work. All these results can bring a new insight to existing LUproblems and solutions to overcome it in advanced technology options.
Source: Lirias
Author: Serbulova, Kateryna
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7111978469
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