A 126.5 dB power supply rejection ratio, 1.02 ppm/°C bandgap reference in 0.18 μm CMOS
Year: 2025
Type: article
Abstract: This paper proposes a high-precision bandgap reference (BGR) architecture targeting advanced process nodes, addressing key challenges of process variations, temperature drift, and power supply noise. The design employs chopping to dynamically suppress operational amplifier offset and low-frequency noise. A pre-regulator stage incorporating cascode current mirrors significantly enhances power supply rejection ratio (PSRR) by isolating external supply disturbances. High-order temperature compensation, implemented through superposition of proportional-to-absolute-temperature (PTAT) and curvature-compensated currents, effectively eliminates the nonlinear thermal drift component of the base-emitter voltage ( ). The core architecture integrates a bandgap core, chopping circuitry, pre-regulator, and fast-startup circuit. Post-layout simulations in CMOS 180 nm technology demonstrate: a temperature coefficient (TC) reduced from 10.52 ppm/°C to 1.02 ppm/°C over −40°C to 125°C, low-frequency PSRR of 126.53 dB at 1 Hz (ranging from 119 dB to 132 dB across process corners), output noise density of 281.56 nV/√Hz at 1 kHz, and output noise of 2.376 at 0.1 Hz–10 Hz. Operating from a 3.3 V supply, the circuit achieves a line regulation of 0.002523%/V and exhibits a fast startup time of 2 μs.
Source: Chip
Authors: MengWei Wu, YuHang Qian, AiLin Yu, Chun Wang, Chi Liu, Guang Yang, Hai Huang
Institution: Harbin University of Science and Technology
Language: English
Subfield: Biomedical Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,000
OpenAlex ID: W7117297384