Work

Automatic tuning based on hardware performance counters and machine learning

Year: 2025

Type: article

Abstract: This paper presents a Machine Learning (ML) methodology for automatically tuning parallel applications in heterogeneous High Performance Computing (HPC) environments using Hardware Performance Counters (HwPCs). The methodology addresses three critical challenges: counter quantity versus accessibility tradeoff, data interpretation complexity, and dynamic optimization needs. The introduced ensemble-based methodology automatically identifies minimal yet informative HwPC sets for code region identification and tuning parameter optimization. Experimental validation demonstrates high accuracy in predicting optimal thread allocation ( > 0.90 K-fold accuracy) and thread affinity ( > 0.95 accuracy) while requiring only 4–6 HwPCs. Compared to search-based methods like OpenTuner, the methodology achieves competitive performance with dramatically reduced optimization time. The architecture-agnostic design enables consistent performance across CPU and GPU platforms. These results establish a foundation for efficient, portable, automatic, and scalable tuning of parallel applications.

Source: Future Generation Computer Systems

DOI: 10.1016/j.future.2025.108358

Authors: Suren Harutyunyan Gevorgyan, Eduardo César, Anna Sikora, Jiří Filipovič, Jordi Alcaraz

Institutions: Universitat Autònoma de Barcelona, Masaryk University, University of Oregon

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

Estimated APC paid: $3,000

Funders: Ministerio de Ciencia, Innovación y Universidades, Ministerstvo Školství, Mládeže a Tělovýchovy, Ministerio de Ciencia e Innovación