ZEROTHLAYER_HCC_BASE v0.2: Production-Grade Governance Architecture for High-Performance Compute
Year: 2026
Type: article
Abstract: Production-ready hardware governance architecture for HPC accelerators (GPUs, AI chips, FPGAs) providing deterministic policy enforcement, immutable audit trails, and fail-closed safety mechanisms. Addresses CMMC Level 3+, DORA, NIS2, AI Act, and ITAR compliance requirements for defense, financial services, and critical infrastructure deployments. Includes complete architecture specification (YAML), reference implementation (Python, 200 LOC), and comprehensive test suite with property-based verification. Core properties verified: evidence-first enforcement, deny-by-default policy, ledger integrity, deterministic replay, fail-closed on ambiguity. Use cases: Defense edge AI, financial HPC, sovereign computing, AI safety infrastructure.
Author: Brueckner, Winfried
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7119014700
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