Year: 2025
Type: article
Abstract: This work focuses on implementation/designing the RISC-V Processor with optimized pipeline throughput, cache hit rate, and dynamic instruction scheduling to enhance the processing speed and energy efficiency. RISC-V extension used to support the tasks in AI, signal processing and cryptography. Design of processor will be implemented by using Verilog/VHDL and simulation tools later it will be tested on FPGA hardware. This project in designing to improve the performance mainly used for high-performance application.
Authors: P. Saiprathyusha, C. Chandrasekhar
Institution: Sri Venkateswara College of Engineering Tirupati
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7127114010
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