Year: 2026
Type: article
Abstract: VLSI floorplanning is a fundamental step in physical design automation that directly impacts chip performance, power consumption, and area utilization. Classic optimization methods include SA, DMT, and PSO; their convergence speeds are rather poor, especially for large-scale designs. This paper addresses both 2D and 3D floorplanning using a Genetic Algorithm (GA). GA represents the floorplans as chromosomes and applies selection, crossover, and mutation to improve block placement iteratively. Experimental comparisons, presented in a two-row tabular format, show that the GA achieves higher efficiency in block placement, wirelength reduction, and computation time compared to SA, DMT, and PSO. The results confirm that GA is indeed one of the effective solutions for large-scale floor planning problems.
Authors: Arulraj Simon Prabu, Mouli G, Aaron Samuel RB
Institution: St. Joseph’s College of Engineering
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7128047327
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