Using Boolean Algebra to Minimize the LUT Count for FPGA Implementation of BCD Adders
Year: 2026
Type: article
DOI: 10.1002/cta.70366
Author: Supriya Aggarwal
Institution: Indian Institute of Information Technology Bhopal
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W7128482710