Year: 2024
Type: dissertation
Abstract: Field Programmable Gate Arrays (FPGAs) can achieve low latency and high throughput inference on Convolutional Neural Networks (CNNs) by implementing dataflow accelerators that pipeline layer-specific hardware to implement an entire network. By implementing a different processing element for each CNN layer, these layer-pipelined accelerators can achieve high compute density but also require a high memory bandwidth. Traditionally this has been satisfied by storing all weights on chip, but this is infeasible for the large CNNs most in need of acceleration. In this work we augment a state-of-the-art dataflow accelerator (HPIPE) to leverage both High-Bandwidth Memory (HBM) and on-chip storage, enabling high performance layer-pipelined dataflow acceleration of large CNNs. We augment the HPIPE architecture and compiler to choose the best data to move to HBM, and automatically generate the required hardware. Compared to the best prior work we obtain speed-ups of 19.4x, 5.1x and 10.5x on ResNet-18, ResNet-50 and VGG-16 respectively.
Source: TSpace (University of Toronto)
Author: Doumet, Mario
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7132881173
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