Work

5500FP: A 24-Trit Balanced Ternary RISC Processor

Year: 2026

Type: article

Abstract: We present the 5500FP, a 24-trit balanced ternary RISC processor implemented on FPGA, with a 120-instruction ISA, native atomic synchronization primitives, and an open hardware development board. The design demonstrates the practical feasibility of balanced ternary computing on modern reconfigurable hardware, providing a concrete platform for research into non-binary architectures without the barrier of custom silicon development.

Source: Zenodo (CERN European Organization for Nuclear Research)

DOI: 10.5281/zenodo.18881737

Author: La Rosa, Claudio Lorenzo

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W7133736749

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