PVT-aware, low-leakage CNFET SRAM with enhanced stability for MIMO systems
Year: 2026
Type: article
Abstract: The increased use and commercialisation of portable battery powered electronic gadgets has made low-power chip designs essential for extending battery life. Low-power electronic circuits also play an important role in the emerging wireless communication systems. Designing appropriate memory circuits is the key for the aforementioned cases, as memory occupies most of the chip area. In this paper, CNFET (Carbon Nanotube Field Effect Transistor)-based low-leakage SRAM (Static Random Access Memory) with enhanced stability is proposed. Simulations are carried out for the proposed CNFETSRAM cell, and its performance is compared with the conventional structures in terms of power, delay, stability, and power delay product by varying PVT (process-voltage-temperature) parameters. According to the results, the hold, read and write stability of the proposed CNFET SRAM improved by 49 %, 85% and 56 %, respectively, as compared to existing memory cells. Furthermore, the hold or leakage power is minimised by up to 99 % compared to conventional SRAMs. The simulation results confirm that the proposed solution is an appropriate memory structure for MIMO systems, meeting the requirements for very large-scale integration (VLSI) circuits with low leakage and high stability.
Source: Acta Polytechnica
Authors: Manickam Kavitha, Ramani S., Sundaravanan Jothiprakasam, Ramakrishnanan Ranjith, Janani P. K.
Institutions: Government of Tamil Nadu, Anna University, Chennai
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W7137282216
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