Design and Implementation of a CNN Core with Integrated Built-In Self-Test (BIST) Architecture on FPGA using Verilog HDL
Year: 2026
Type: article
Abstract: Retraction NoticeTitle: Design and Implementation of a CNN Core with Integrated Built-In Self-Test (BIST) Architecture on FPGA using Verilog HDLInternational Journal of Electrical and Electronics Research, ISSN 2348-6988 (online)Vol. 14, Issue 1, January 2026 - March 2026, Page No: 26-38Published Date: 20-March-2026Retraction Date: 29 May 2026 Reason for Retraction: On the author's request
Author: retracted
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
Funder: Delhi Technological University
OpenAlex ID: W7140680705
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