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A Lightweight Hardware Security SoC for Fabless

Year: 2026

Type: article

Abstract: This paper presents the design and verification of SiliconForge Security SoC V3.0, a lightweight hardware security SoC targeting Fabless tapeout on the SKY130 open-source process. The design integrates three hardware security primitives: a 64-stage RO-PUF generating a 64-bit chip-unique fingerprint (Hamming weight=32/64), a 6-state anomaly detection FSM with zero-cycle alert latency and dual-threshold locking, and an ARX hash engine producing a 128-bit identity token with Phys-XOR audit chain. All modules verified using Icarus Verilog 12.0 on EDA Playground: 61 test cases, 100% pass rate on core modules, zero latch inferences. Targeting ChipFoundry shuttle CI2609.

Source: Zenodo (CERN European Organization for Nuclear Research)

DOI: 10.5281/zenodo.19303074

Author: maomaoati-coder

Language: English

Topic: Physical Unclonable Functions (PUFs) and Hardware Security

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W7142977680

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