Planar FD-SOI nMOSFETs with a 60.5 mV/dec subthreshold swing and 11-order ON/OFF ratio enabled by a resist-less process
Year: 2026
Type: article
Abstract: Fully depleted silicon on insulator (FD-SOI) MOSFETs were fabricated with an exceptionally low body factor (γ) of 0.008 and a minimal SiO2/Si interface trap density (DIT) of 6.89 × 109 eV−1 cm−2. These devices achieved a record-low subthreshold swing (SS) of 60.5 ± 0.1 mV/dec and ON/OFF current ratio exceeding 11 orders of magnitude. The superior switching performance is attributed to the Fermi level (EF) moving exclusively within the midgap region—where the interface state density is lowest—during ON/OFF transitions. This mechanism maintains a stable SS plateau over two orders of magnitude of drain current (IDS) and effectively suppresses gate-induced drain leakage, leading to the record-low IOFF. Furthermore, the use of a simple, rapid, and resistless fabrication process involving metal mask sputtering for film patterning prevented sample contamination, ensuring minimal characteristic deviation even in an uncontrolled environment. These results demonstrate that optimized planar FD-SOI architectures can provide gate controllability and performance comparable to advanced three-dimensional transistor structures.
Source: APL Electronic Devices
DOI: 10.1063/5.0320658
Authors: Wenchang Yeh, Ryota Nosu
Institution: Shimane University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W7147594014