Year: 2026
Type: article
Abstract: Peripheral Component Interconnect Express (PCIe) is a critical interface for FPGA-based accelerators, yet existing controller solutions are often proprietary, costly, and/or incompatible with open-source workflows. We present a fully open-source PCIe controller, written in synthesizable Verilog and optimized for Field-Programmable Gate Array (FPGA) deployment. The core is verified using a Python-based cocotb2.0.1 and pyuvm4.0.0 testbench with a modeled Root Complex (RC), complete with data packet generation, automated checks for enumeration, flow control, and retry mechanisms. On an AMD Xilinx AC701 (XC7A200T), the design achieves less than 6% LUT utilization, timing closure at 100 MHz user clock, and demonstrates compatibility with vendor transceivers. Reference builds also meet timing on Altera Agilex devices with similar resource utilization. All RTL, verification infrastructures, and example designs are publicly released, enabling reproducible research and accelerating the development of PCIe-enabled systems for high-speed data acquisition, NVMe front-ends, and custom FPGA accelerators.
Source: Applied Sciences
DOI: 10.3390/app16073409
Authors: Somoye Idris, David Jovel, Lamia Mannan
Institution: Morgan State University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,896
Funder: Morgan State University
OpenAlex ID: W7147625288