Heterogeneous architectures enable a 138 × reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting
Year: 2026
Type: article
Abstract: Quantum computer hardware performance and scale have accelerated rapidly over the past few years, enabling real workloads to be run using hundreds of physical qubits, and industry roadmaps predict systems with hundreds of thousands of qubits coming online in the next decade. Moving to this scale requires major advances in quantum error correction (QEC) and its useful integration into real hardware systems. Despite significant theoretical and experimental QEC progress, quantum computer architecture has suffered a significant gap, with bottom-up physical-device-driven challenges largely disconnected from top-down QEC-code-driven considerations. In this work, we unify these two views, presenting a complete heterogeneous quantum computing architecture incorporating task-specific hardware selection and QEC encoding, and agnostic to code selection or physical qubit parameters. The architecture is based on the observation that due to the lengthy idling periods encountered in common algorithms, it can be advantageous to separate quantum processing operations from quantum memory, enabling expanded flexibility in qubit modality and code choice between subsystems. Our approach further enables special-purpose processing modules, and includes a full microarchitecture for fault-tolerant implementation of interfaces between quantum processing units and quantum memories. Using this architecture and a new fully featured compiler functioning across subsystems at the scale of 1000 logical qubits, we schedule and orchestrate a variety of algorithms down to hardware-specific instructions; a detailed accounting of all operations reveals up to 551 × reduction in algorithmic logical error and up to 138 × reduction in physical-qubit overhead compared to a monolithic baseline architecture. We then consider the factorization of 2048-bit RSA-integers; using an experimentally demonstrated grid-coupling topology, factoring RSA-2048 requires 381k physical qubits and 9.2 d, which can be reduced to 4.9 d via addition of an algorithm-specific accelerator for the Adder subroutine (requiring 439k qubits). Finally, assuming hypothetical long-range coupling, implementing quantum memory using qLDPC codes reduces the resources required for factoring to just 190k qubits and under 10 d. These results and the tooling we have built indicate that heterogeneous quantum-computer architectures can deliver significant, verifiable benefits on realistic hardware.
Source: New Journal of Physics
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,610
OpenAlex ID: W7152606348