A study on propagation delay and power dissipation of a 2-bit CMOS magnitude comparator with critical path evaluation
Year: 2026
Type: article
Abstract: This work presents the design of 2-bit magnitude comparator in Cadence Virtuoso tool using gpdk090 technology. The detailed analysis of propagation delay and power dissipation (both dynamic and static power) for its outputs—L (A < B), E (A = B), and G (A > B) are analysed. The comparator was simulated and evaluated to quantify delay and power behaviour under varying conditions. Results show that the L (AB) outputs incur higher delays of 74.99 ns and 49.20 ns due to longer critical paths. Further, Results reveal that the L (AB) output demonstrates moderate dynamic power of 8.11 mW but records the highest static leakage of 3.92 µW, arising from device sizing and threshold voltage trade-offs to enhance timing performance. These findings establish that equality detection is the most energy-intensive operation, while greater-than logic suffers from elevated leakage currents. The study provides critical insights into the relationship between logic structure and power characteristics, offering guidance for targeted low-power design strategies in comparator circuits and similar digital building blocks.
Institution: Manipal Academy of Higher Education
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7154590724
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