Year: 2026
Type: preprint
Abstract: Real-world graph applications are generally larger than the size of the cache itself. Due to this reason, the memory hierarchy was identified as a key bottleneck by the earlier works. Undoubtedly, the performance can be achieved by improving cache, there is still a scope for performance gain by improving branch prediction accuracy. In graph processing applications, the occurrence of branch mispredictions is very frequent and is a major limitation for the overall performance. Within a program, there are different kinds of branches that recur throughout its execution. Although lots of branch predictors (BP) have been developed earlier to capture the static and dynamic behavior of branches. Branch predictors can yet be further optimized to handle the branches that cause mispredictions.
Source: arXiv (Cornell University)
Authors: Upasna, Tavva, Venkata Kalyan
Institution: Indian Institute of Technology Ropar
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7155198310
Cites:
Cited by:
Related to: