ODCGate: Leveraging Observability Don't Care Conditions for Enhanced Power Efficiency in Clock Gating
Year: 2026
Type: article
Abstract: Clock gating reduces dynamic power by integrating activation functions and integrated clock gating (ICG) cells into the clock path, selectively disabling the clock signal to register when unnecessary. While conventional activation function extraction methods rely on manual design or register-transfer level analysis, a gate-level alternative exists: deriving activation functions through the extraction of observability don’t care (ODC) conditions from the underlying netlist. This paper presents ODCGate , a framework designed to automatically detect ODC conditions as the activation functions and safely block clock transitions for unused registers, thereby further reducing dynamic power consumption during clock gating. The computation begins with cut boundary enumeration and simulation. To further minimize additional PPA overhead, we apply hybrid simplification techniques to the extracted logic, and enable sharing among registers through clustering. Experimental results show that, beyond the clock gating optimization of a commercial logic synthesis tool, our method achieves an average 33.46% additional reduction in dynamic power, with minimal impact on other PPA metrics.
DOI: 10.1145/3812543
Institution: Chinese University of Hong Kong
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7155644203