Projetando e testando aceleradores de IA baseados em APSoC tolerantes a falhas para aplicações aeroespaciais
Year: 2025
Type: dissertation
Abstract: The rapid advancement of deep learning in both complexity and adoption has increased the demand for efficient hardware capable of handling the computational requirements of Convolutional Neural Networks (CNNs). Static Random Access Memory (SRAM)-based All Programmable System on Chips (APSoCs) have become a promising platform for deploying Artificial Intelligence (AI) inference engines due to their flexibility, low latency, and power efficiency. However, when commercial SRAM-based APSoCs are used in safety-critical missions operating in radiation-prone environments, they become vulnerable to radiation-induced Single Event Effects (SEEs), which can compromise system reliability and adversely affect mission success. As a result, design optimizations aimed at improving efficiency and performance, together with fault-tolerant strategies to enhance reliability, become essential to meet the stringent requirements of APSoC-based AI accelerators in safety-critical applications. In this context, this thesis presents a case-study implementation of the open-source ZynqNet AI inference engine, written in C++, optimized with directive pragmas and generated via High Level Synthesis (HLS). A four-layer CNN trained on the SAT-6 dataset was deployed on the Zynq-7000 APSoC (xc7z020clg484-1), with the Programmable Logic (PL) implementing ZynqNet and the Processing System (PS) managing execution via the Cortex-A9 processor. Quantization techniques were applied to reduce area and power, moving from floating-point to fixed-point and eventually 8-bit integer arithmetic, with different numbers of processing elements to exploit task parallelism. Performance was improved by packing eight 8-bit integer values to enable parallel 64-bit read and write operations, which led to the design and implementation of small caches, reducing the number of clock cycles required to access the data in the external Double Data Rate (DDR) memory. Communication architectures were also designed to optimize data exchange between the accelerator and the external DDR memory, with optional Level 1 Data (L1D) and Level 2 (L2) cache usage. A comprehensive analysis of CNN performance and Field Programmable Gate Array (FPGA) resource usage across configurations was conducted. Then, a fault injection methodology enabled rapid, cost-efficient evaluation of ZynqNet’s reliability, identifying components most vulnerable to radiation faults. Coarse Grained, Modular and Distributed Triple Modular Redundancy (TMR) techniques were applied at the design level to mitigate Single and Multiple Bit Upsets in the configuration memory, alongside Error Detection and Correction (EDAC) mechanisms were integrated into the Block RAMs (BRAMs) of the ZynqNet’s Caches blocks. To address persistent bit flips in the FPGA’s Configuration Memory (CRAM), the memory scrubbing mechanism was enabled for detection and correction of radiation-induced faults during the CNN computing. Radiation testing using heavy ions was conducted on both unmitigated and hardened designs to validate fault tolerance. Reported results include reliability curves, and the following metrics: Mean Faults to Failure (MFTF), Mean Fluence to Failure (MΦTF), Dynamic Cross Section (σ), and hardware design evaluation metrics such as area, power and performance. The study offers valuable insights into the trade-offs between resource usage, power, performance and reliability for the case-study ZynqNet accelerator in radiation-prone environments.
Author: Aguilar, Eduardo Domingo Marañon
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
Awards: G1783288283, G3671023231
OpenAlex ID: W7155670870