Year: 2026
Type: article
Abstract: Background/Objectives: In this paper, we implemented the neural network of learning based filtering algorithm, which eliminates noise generated by ray-tracing, through Verilog HDL. Methods/Statistical analysis: The neurons used in the learning based filtering algorithm are divided into five stages: IDLE, SIGN, MUL, SUM, and ACT. Each stage is processed in one cycle through the FSM(Finite State Machine).These neurons were organized into a number of layers. The operation used fixed point. Findings: The neural network has a large amount of computation, but since the computation is simple, it can be processed quickly by hardware implementation. It has a hidden layer (10 neurons with 36 inputs), an output layer (6 neurons with 10 inputs), each layer has 5 stages, so you can get the filtering parameters after 10 cycles. Improvements/Applications: Verilog HDL can be synthesized and downloaded to the FPGA to operate up to 185MHz.
Authors: Seong-Hyeon Han, Kwang-Yeob Lee
Institution: Seokyeong University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
Awards: G3922194683, G7144874585
OpenAlex ID: W7155685060