Work

Reliability assessment of Z-shaped gate TFET under interface trap charges and thermal variations for low-power applications

Year: 2026

Type: article

Abstract: This work investigates the reliability of a Z-shaped gate elevated-source TFET (ZG-ES-TFET) by examining the effects of interface trap charges (ITCs) and ambient temperature variations on its DC and analog/RF performance. ITC polarities and densities in the range 5 × 1012–1 × 1013 cm− 2 at the oxide–semiconductor (O–S) interface are considered. Compared with the trap-free case, ITCs cause significant variations in ON-current, off-state leakage, and average subthreshold swing (SSavg), particularly at lower gate voltages. In particular, an increase in donor trap density from 5 × 1012 to 1 × 1013 cm− 2 leads to enhanced transconductance, which subsequently improves the cut-off frequency and reduces the transit time. The effect of ambient temperature on device performance is further examined over the range of 250 K to 400 K under different trap conditions. TCAD-based simulations reveal that temperatures exceeding 300 K cause a notable increase in off-state leakage, primarily due to the enhanced contribution of Shockley–Read–Hall and trap-assisted tunneling mechanisms in the subthreshold regime. Consequently, both DC and analog/RF performance of ZG-ES-TFET degrade at elevated temperatures, whereas in the superthreshold region, the dominance of band-to-band tunneling renders the impact of temperature and ITCs comparatively insignificant.

Source: Scientific Reports

DOI: 10.1038/s41598-026-48301-z

Authors: Tammisetti Ashok, Chandan Kumar Pandey

Institution: VIT-AP University

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: gold

Estimated APC paid: $2,690

Funder: VIT University