High-performance posit arithmetic for accelerating big data using machine learning algorithm with highly pipeline architecture in breast cancer identification
Year: 2026
Type: article
Abstract: One of the deadliest diseases that affects women is breast cancer, so accurate diagnosis becomes an essential element in reducing the risk of mortality in their lives. The proposed method incorporates a posit-based support vector machine (SVM) linear classifier system at each stage to increase the accuracy of breast cancer prediction with respect to unclassified data by iteratively processing outlier data. Several conventional diagnostic methods are utilized to reduce the number of cases that are misclassified. To accelerate data classification and reduce the cost of cancer diagnosis, numerous researchers have been striving to integrate machine learning algorithms, such as SVM linear classifiers, into their designs using modern high-speed field-programmable gate arrays (FPGAs). The suggested system attained a very good accuracy of 97.19% (553 true out of 569 patients) using posit arithmetic with 24-bit representation compared to 91.08% using conventional 32-bit IEEE 754 floating-point format, with 80% of training and 20% of test data. In other words, posit reduces the incorrect diagnoses by a factor of 3, from 9% to about 3%. The findings show that the 24-bit posit arithmetic also yields faster data classification compared to the 32-bit IEEE 754 float arithmetic in breast cancer detection. The IEEE 754-2008 compliant floating-point unit (FPU) can be replaced by a Posit Arithmetic Unit (PAU) due to itss higher accuracy, speed, and simpler hardware design. The 24-bit PAU is evaluated through simulation and logic synthesis design using the Vivado software. An SVM classifier with the PAU is designed through the Verilog HDL language, and then area, power, and timing are calculated. The design is developed using the KC705 evaluation kit that operates on the Xilinx Kintex™-7 FPGA KC705 platform. The posit model accelerates data processing by using only 720 bits for each patient instead of 960 bits for the conventional float method. The power analysis from the implemented netlist shows a total on-chip power of 0.318 W, a junction temperature of 26.4 °C, and a thermal margin of 12.7 W with medium confidence level. The total on-chip power of 0.321 W has dynamic power of 0.224 W and device static power of 0.094 W. With posit implementation, there is a slight reduction in power consumption with respect to total on-chip power and dynamic power. The timing result obtained indicates that there is no timing violation and it can perform with a worst negative slack (WNS) of about 57.994 ns before the clock is set, and hold timing analysis indicates worst hold slack of 0.204 ns. A key advantage of 24-bit posit over 32-bit IEEE floats is that posit environments support exact dot products and IEEE floats do not.
Source: Measurement
Language: English
Subfield: Computational Theory and Mathematics
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $3,760
OpenAlex ID: W7160503261