Work

Shared L1 Cache Architecture Between Multiple CPU Cores

Year: 2026

Type: article

Abstract: A prior art disclosure describing a CPU cache architecture in which Level 1 (L1) cache is partitioned into a dedicated per-core region and a shared inter-core region, enabling direct data sharing at the L1 cache level. Conceived independently by the inventor on May 23, 2026.

Source: Zenodo (CERN European Organization for Nuclear Research)

DOI: 10.5281/zenodo.20357076

Author: M vaghela, Jagrav

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W7162205974

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