Work

Design of 8‐Bit Dadda Multiplier and Divider Using Logic Level Pruning Approximate Arithmetic Circuits

Year: 2026

Type: article

Source: International Journal of Numerical Modelling Electronic Networks Devices and Fields

DOI: 10.1002/jnm.70182

Authors: Kattekola Naresh, Shubhankar Majumdar, Y. Padma Sai

Institution: National Institute of Technology Meghalaya

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: Ministry of Electronics and Information technology, Department of Telecommunications, Ministry of Communications, India

Awards: G2275543156, G5485593050

OpenAlex ID: W7165032264

FWCI:

Cites: 16

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