A 10-Bit Successive Reference Approximation ADC Enabled By Switched-Capacitor Dynamic Reference Generation With Pipelined Pre-charging And Voltage Ripple Cancellation
Year: 2026
Type: conference-paper
Abstract: This paper introduces an ADC architecture that employs a cascaded switched-capacitor DC-DC chain for dynamic reference generation, realizing a successive reference approximation (SRA) technique. This approach tackles the critical challenges of exponential growth in total capacitance and power consumption encountered in traditional CDAC arrays-based ADC at higher resolutions. Furthermore, the paper proposes a pipelined pre-charging technique for fast settling and a voltage ripple cancellation scheme to enable a high sampling rate, which collectively enhance conversion speed and reduce the overall capacitor area of the proposed ADC. The prototype ADC is designed in a 0.18 µm CMOS process and occupies an active area of 0.043 mm2. At a 1.8 V supply and 5.12 MS/s sampling rate, post-layout simulation results show that the ADC achieves an SNDR of 48.9 dB and SFDR of 57.1 dB, and consumes 180 µW, resulting in a figure of merit (FoM) of 154.5 fJ/conversion-step.
Institution: Shanghai Jiao Tong University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7165123922